1. Field of the Invention
The present invention relates to a control circuit for a solid state image sensing device, and more particularly to a control circuit for a solid state image sensing device which is capable of reading out signal charge in either field storage system or frame storage system and is provided with an electronic shutter for controlling a signal charge storage time (i.e., exposure time) by shutter pulses for discharging charges, in which timings of readout gate pulses within each field period are offset from each other between pixels in even rows and pixels in odd rows upon readout in the field storage system.
2. Description of the Prior Art
In general, a solid state image sensing device such as a CCD (Charge Coupled Device) is designed so that a signal charge stored in each photo sensor (pixel) within the solid state image sensing device is discharged toward an overflow drain region or a semiconductor substrate by the application of shutter pulses and an exposure time may be changed by adjusting a charge storage time in a field period by the application of the shutter pulses.
In general, the control of the charge storage time by the shutter pulses is performed in every 1H (horizontal period) unit. This is because the timing of application of the shutter pulses is limited within a horizontal fly-back line period. The reason for the limitation of the shutter pulse application timing in the horizontal fly-back line period is that a noise is prevented from being entrained into a video signal.
Among video cameras using such solid state image sensing devices, there are some cases where such a signal charge storage time controlling function is utilized in an iris control.
Recently, such an iris control technique has been considerably developed. In order to enlarge a dynamic range in the iris control, also in a vertical blanking period, the shutter pulses may be generated until readout pulses are generated. In addition, a technique has been developed in which, in the vertical blanking period, the shutter pulse generation period is much shorter than the 1H period and the signal charge storage time is finely controlled in a unit time much shorter than the 1H period. This is proposed in, for example Japanese Patent Application No. Hei 4-235397.
Irrespective of whether or not the signal charge storage time is controlled by the shutter pulses, there are two systems, i.e., a field storage system and a frame storage system for reading out signal charges of an interline type solid state image sensing device. In the frame storage system, in an odd field, signal charges of pixels in odd rows of every two rows in the vertical direction in a period of field shift are transferred to vertical transfer registers, and subsequently, a line shift is effected so that the signal charges of pixels in the odd rows are read out in order from the output end. Meanwhile, the signal charges are stored in pixels in even rows, and subsequently, in an even field, the signal charges of the pixels in the even rows are transferred to the vertical transfer registers. Then, the line shift is effected so that the signal charges of the respective pixels in the even rows are read out in order from the output end.
In contrast, in the field storage system, for example, in the odd field, signal charges of pixels of the odd row counted from the horizontal transfer registers and the next, i.e., even row are simultaneously read out so that the signal charges in a pair of upper and lower pixels are mixed and transferred in the vertical transfer registers, whereas in the even field, a combination of rows to be mixed in the vertical transfer registers is made different from that in the odd field case, so that signal charges of pixels of the even row counted from the horizontal transfer registers and the next, i.e., odd row are mixed and transferred in the vertical transfer registers.
In such a field storage system, it is possible to read out the signal charges of all the pixels in the image sensing region in every field.
The field storage system and the frame storage system have merits and demerits. For this reason, there are many solid state image sensing devices in which the storage systems may be switched over between the field and frame storage systems.
In an overall system in which the storage system for signal charges may be switched between the field storage system and the frame storage system, in the frame storage, as shown in FIG. 5, the readout pulse generation timing in the even field is different from that in the odd field in each field period, and as a result, there is a time lag in signal charge storage time to generate flickers.
This problem will be explained in more detail.
Namely, the readout of the signal charges to the vertical transfer registers from the respective photo sensitive elements (sensors) each of which constitutes a pixel in the solid state image sensing device is performed by much more increasing a potential well of the vertical transfer registers than the vertical transfer registers is normally operated. Incidentally, the potential well of the readout gate has to be deep during the readout operation. However, if the potential well of the vertical transfer registers is made deeper by the readout gate pulses kept at a high level, the potential well at the readout gate portion per se is deeper in accordance with the change of the increase of the potential well of the registers. Accordingly, it is unnecessary to provide a special process to make the potential well of the readout gate deeper.
By the way, as described above, in the frame storage system, in each field, the signal charges are read out always only for half the pixels, whereas in the field storage system, the signal charges are read out for all the pixels in every field.
Accordingly, if in the field storage, the signal charges are all read out from all the pixels at once, as shown in FIG. 6, the potentials of a portion under a vertical transfer electrode V1 which receives .PHI.V1 of vertical transfer four-phase clock pulses .PHI.V1 to .PHI.V4 and a portion under a vertical transfer electrode V3 which receives .PHI.V3 are remarkably reduced and the ground line is subjected to this effect so that the potential of the ground line is also reduced. (Incidentally, FIG. 6 shows as if the pulses .PHI.V1 to .PHI.V4 are applied only to the transfer electrodes of the vertical transfer registers at the right side but this is for simplification and actually the pulses are applied to all the vertical transfer registers.). This is because the ratio of the vertical transfer registers to the image sensing region of the solid state image sensing device is large and when the potentials of the registers are largely varied, the entire solid state image sensing device is affected.
For this reason, even if the potentials of the vertical transfer registers are made deeper, the potentials of the image sensing region as a whole are deeper together. As a result, there is a fear that it would be difficult or impossible to read out the signal charges. Therefore, when the pulse .PHI.V1 is raised, the pulse .PHI.V3 should be lowered, whereas when the pulse .PHI.V3 is raised, the pulse .PHI.V1 should be lowered, thereby keeping the potential of the ground line constant. Therefore, during the field storage, it is necessary to somewhat offset the two readout gate pulse generation timings from each other.
Subsequently, in case of the frame storage, only the pixels in every two rows in each field are read out. Accordingly, only one readout gate pulse is generated for one field. Consequently, there is no problem even if the readout gate pulses for the odd and even fields are generated at the same time.
However, if the readout gate pulse generation timings are different between the field storage and the frame storage, it is necessary to provide discretely readout gate pulse generation circuits for the field storage and the frame storage. Accordingly, the same readout gate pulse generation circuit is used commonly for the field storage and the frame storage to generate the readout gate pulse.
As a result, the generation timings within the fields are offset between the readout pulse for the even rows and the readout pulse for the odd rows during the frame storage. The reason why this causes the generation of flicker will be explained with reference to FIG. 5.
As described above, during the frame storage, the readout of the signal charges from the pixels is effected only for one of the odd row and the even row in each field period. However, since the readout gate pulse generation is effected by the same circuit for both the field storage and the frame storage, the readout gate pulse generation timings between the odd field and the even field in each field period are offset by Ta.
In contrast, the timings of shutter pulse Vsub are kept unchanged between the odd field and the even field. Accordingly, even if the same signal charge storage time is assigned, a time lag Ta in signal charge storage time between the final shutter pulse Vsub1 and the subsequent readout gate pulse is generated between the odd field and the even field. This of course causes a difference in brightness to generate the flicker.
However, the time lag Ta is actually about one millionth second, for example. Accordingly, under the condition that the signal charge storage time is relatively long, the difference in the signal charge storage time of one millionth second is essentially negligible. In this case, there is no visible flicker. On the other hand, when the signal charge storage time is short, the time lag Ta causes a remarkable change in brightness between the odd field and the even field. In particular, in a solid state image sensing device in which a shutter pulse is generated even in a vertical blanking period, and in addition, the shutter pulse generation period in the vertical blanking period is much shorter than the 1H period so as to ensure a super high speed shutter effect, the shorter the storage time (exposure time), the more the flicker will be generated to reduce the quality of the image would remarkably deteriorate. Therefore, in this case, a problem that the flicker will be generated during the frame storage could not be negligible.